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MIC4223/MIC4224/MIC4225
Dual 4A, 4.5V to 18V, 15ns Switch Time, Low-Side MOSFET Drivers with Enable
General Description
The MIC4223/MIC4224/MIC4225 are a family of a dual 4A, High-Speed, Low-side MOSFET drivers with logic-level driver enables. The devices are fabricated on Micrel's Bipolar/CMOS/DMOS (BCD) process and operate from a 4.5V to 18V supply voltage. The devices parallel Bipolar and CMOS output stage architecture provides high-current throughout the MOSFETs Miller Region allowing the driver to sink and source 4A of peak current from a 12V supply and quickly charge and discharge a 2000pF load capacitance in under 15ns, while allowing the outputs to swing within 0.3V of VDD and 0.16V of ground. The MIC4223/MIC4224/MIC4225 driver and enable inputs feature TTL and CMOS logic-level thresholds which are independent of supply voltage. Each driver features a dedicated active-high enable input which is internally pulled high to VDD through 100k, allowing the pins to be left unconnected if it is not required to disable the driver outputs. The driver inputs have been designed to protect against ground bounce and are protected to withstand -5V of voltage swing at -40mA. Driver outputs are also protected to withstand 500mA of reverse current. The MIC4223/MIC4224/MIC4225 are available in three configurations using industry standard pin out; dual inverting (MIC4223), dual non-inverting (MIC4224) and complimentary (MIC4225). They are available in 8-pin SOIC and thermally enhanced e-PAD 8-pin MSOP and support operating junction temperatures from -40C to +125C.
Features
* 4.5V to 18V supply voltage operating range * High peak source/sink current - 3A at VDD = 8V - 4A at VDD = 12V * 15ns/15ns Rise and Fall times with 2000pF load * 25ns/35ns (Rising/Falling) input propagation delay * 20ns/45ns (Rising/Falling) enable propagation delay * Active-high driver enable inputs with 100k pull-ups * CMOS and TTL logic input and enable thresholds independent of supply voltage * Driver input protection to -5V at -40mA * Output Latch-up protection to >500mA reverse current * Industry standard pin out with two package options - ePAD MSOP-8 (JA = 60C/W) - 8-pin SOIC (JA = 120C/W) * Available in dual-inverting (MIC4223), dual noninverting (MIC4224) and complementary (MIC4225) * Dual output drive by paralleling channels * -40C to +125C operating junction temperature range
Block Diagram
Applications
* * * * * * * * High-Efficiency MOSFET switching Switch mode power supplies DC-to-DC converters Motor and solenoid drivers Clock and line drivers Synchronous rectifiers Pulse transformer drive Class D switching amplifiers
Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
June 2009
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Ordering Information
Part Number MIC4223YM MIC4223YMME MIC4224YM MIC4224YMME MIC4225YM MIC4225YMME Configuration Dual Inverting Dual Inverting Dual Non-inverting Dual Non-inverting Inverting + Non-inverting Inverting + Non-inverting Junction Temp. Range -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C Package 8-pin SOIC 8-pin EPAD-MSOP 8-pin SOIC 8-pin EPAD-MSOP 8-pin SOIC 8-pin EPAD-MSOP Lead Finish Pb-Free Pb-Free Pb-Free Pb-Free Pb-Free Pb-Free
Pin Configuration
8-Pin SOIC (YM) 8-Pin ePAD MSOP (YMME)
8-Pin SOIC (YM) 8-Pin ePAD MSOP (YMME)
8-Pin SOIC (YM) 8-Pin ePAD-MSOP (YMME)
Pin Description
Pin Number 1 Pin Name ENA Pin Function Enable pin for output A. TTL/CMOS-compatible logic input. A logic-level high enables the device. An internal pull-up enables the part if pin is open. A logic-level low disables the device and the output will be low regardless of the input state. Control Input A: TTL/CMOS-compatible logic input. Connect to VDD or ground if not used and connect ENA to ground to disable driver A. Ground Control Input B: TTL/CMOS compatible logic input. Connect to VDD or ground if not used and connect ENB to ground to disable driver B. Output B: Parallel Bipolar/CMOS output. Voltage Supply Input: +4.5V to +18V Output A: Parallel Bipolar/CMOS output. Enable pin for output B. TTL/CMOS-compatible logic input. A logic-level high enables the device. An internal pull-up enables the part if pin is open. A logic-level low disables the device and the output will be low regardless of the input state. Exposed thermal pad for ePad MSOP package only (Not available on SOIC-8L package). Connect to ground. Must make a full connection to the ground plane to maximize thermal performance of the package.
2 3 4 5 6 7 8
INA GND INB OUTB VDD OUTA ENB
EP
GND
June 2009
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Micrel, Inc.
MIC4223/MIC4224/MIC4225
Absolute Maximum Ratings(1)
Supply Voltage (VDD)....................................................+20V Input Voltage (VINA, VINB) ................ VDD + 0.3V to GND - 5V Enable Voltage (VENA, VENB)............... ...0.3V to VDD + 0.3V Junction Temperature (TJ) .........................-55C to +150C Storage Temperature ................................-65C to +150C Lead Temperature (10 sec.)....................................... 300C ESD Rating................................. HBM = 2kV, MM = 200V(3)
Operating Ratings(2)
Supply Voltage (VDD)..................................... +4.5V to +18V Junction Temperature (TJ) ........................ -40C to +125C Package Thermal Resistance EPAD MSOP (JA) .............................................60C/W SOIC (JA) ........................................................120C/W
Electrical Characteristics
4.5V VDD 18V; CL = 2000pF. TA = 25C, bold values indicate full operating junction temperature range, unless noted.
Symbol Input VIH VIL Hysteresis IIN Input Current 0 VIN VDD VIN = -5V Output VOH VOL RO IPK I tR tF tD1 tD2 VEN_H VEN_L Hysteresis REN tD3 tD4 ISH ISL Enable Impedance Propagation Delay Time Propagation Delay Time Power Supply Current Power Supply Current VDD = 18V, VENA = VENB = GND CL = 2000pF CL = 2000pF VINA = VINB = 3.0V, VENA = VENB = open VINA = VINB = 0.0V, VENA = VENB = open High Output Voltage Low Output Voltage Output Resistance - Source Output Resistance - Sink Peak Output Current Latch-Up Protection Rise Time Fall Time Delay Time Delay Time High Level Enable Voltage Low Level Enable Voltage IOUT = -10mA, VDD = 18V IOUT = 10mA, VDD = 18V IOUT = -10mA, VDD = 18V IOUT = 10mA, VDD = 18V VDD = 8V VDD = 12V Withstand reverse current Test Figure 1; CL = 2000pF Test Figure 1; CL = 2000pF Test Figure 1; CL = 2000pF Test Figure 1; CL = 2000pF LO to HI transition HI to LO transition 2.4 Switching Time 15 15 25 35 1.9 1.55 0.35 100 20 45 1.7 0.7 60 150 2.5 1.5 0.8 40 40 45 50 ns ns ns ns V V V k ns ns mA mA 30 16 3 4 >500 mA VDD - 0.45 0.30 45 30 V V A -1 -10 -40 Logic 1 Input Voltage Logic 0 Input Voltage 2.4 2.2 1.95 0.25 1 10 0.8 V V V A A mA Parameter Condition Min Typ Max Units
Enable (ENA, ENB)
Power Supply
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
June 2009
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MIC4223/MIC4224/MIC4225
Test Circuit
Figure 1. Test Circuit
Timing Diagram
Inverting Driver
Non-Inverting Driver
Enable to Output Timing Diagram
June 2009
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MIC4223/MIC4224/MIC4225
Typical Characteristics
Conditions: TA =25C.
VINA, B Threshold vs. VDD
2.2 2.15
2.3 2.2
VINA, B Threshold vs. Temperature
2.0
VENA, B Threshold vs. VDD
VDD =12V
Threshold (V)
2.1 2.05 2 1.95 1.9 1.85 1.8 4 6 8 10 12
VIH
1.8
VEN_H
2.1 2.0 1.9 1.8 1.7
VIH
1.6 1.4
VEN_L
VIL
VIL
1.2 1.0
-40 -20 0 20 40 60 80 100 120 140
14
16
18
VDD (V)
Temperature (C)
4
6
8
10
12
14
16
18
VDD (V)
Enable Threshold vs. Temperature
2.1 2.0
IDD vs. VDD (Disabled)
1.2
IDD vs. VDD (Enabled)
1.4
VDD =12V
1.0
VINA = VINB = VDD
1.2 1.0
VINA = VINB = VDD
Threshold (V)
1.9 1.8 1.7 1.6 1.5 1.4 1.3
-40 -20 0 20 40 60
VEN_H
IDD (mA)
0.6 0.4
IDD (mA)
0.8
0.8 0.6 0.4 0.2 0.0
VINA = VINB = 0
VINA = VINB = 0
VEN_L
0.2 0.0
80
100 120 140
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
Temperature (C)
VDD (V)
VDD (V)
IDD vs. Temperature (Disabled)
1.2 1.0 1.4
IDD vs. Temperature (Enabled)
4.0
IDD vs. Temperature (Switching)
3.5 3.0
VDD = 12; VIN = VDD
VDD = 12; VIN = VDD
1.2 1.0
IDD (mA)
IDD (mA)
VDD = 4.5V; VIN = VDD
0.8 0.6 0.4
IDD (mA)
0.8 0.6 0.4 0.2
VDD = 4.5; VIN = VDD
2.5 2.0 1.5 1.0
VDD = 12; VIN = 0
VDD = 12V; VIN = 500kHz
VDD = 12V; VIN = 0
VDD = 4.5V; VIN = 0
0.0
-40 -20 0 20 40 60 80 100 120 140
0.2 0.0
-40
VDD = 4.5V; VIN = 0
-20 0 20 40 60 80 100 120 140
0.5 0.0
-40 -20 0
VDD = 4.5V; VIN = 500kHz
20 40 60 80 100 120 140
Temperature (C)
Temperature (C)
Temperature (C)
IDD vs. Frequency (VDD = 5V)
Both Drivers Switching
50 40 30 20 10 180 160 140
IDD vs. Frequency (VDD = 5V)
Both Drivers Switching
120 100
IDD vs. Frequency (VDD = 12V)
Both Drivers Switching
IDD (mA)
IDD (mA)
120 100 80 60 40
IDD (mA)
2.2nF 1nF
10nF 4.7nF
80 60
2.2nF
1nF
40 20
470pF
0 0 500 1000 1500 2000
20 0 0 500 1000 1500 2000
470pF
0 0 500 1000 1500 2000
Frequency (kHz)
Frequency (kHz)
Frequency (kHz)
June 2009
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M9999-061109-A (408) 944-0800
Micrel, Inc. Conditions: TA = 25C.
IDD vs. Frequency (VDD = 12V)
Both Drivers Switching
140 120 100
MIC4223/MIC4224/MIC4225
IDD vs. VDD (CL = 2.2nF)
Both Drivers Switching
20 18 16
120
IDD vs. VDD (CL = 2.2nF)
Both Drivers Switching
200kHz
100
IDD (mA)
80 60 40 20 0 0 200 400 600
4.7nF
IDD (mA)
12 10 8 6 4 2 0
100kHz
IDD (mA)
10nF
14
2MHz
80 60 40
1MHz
50kHz
500kHz
20 0
800
1000
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
Frequency (kHz)
VDD (V)
VDD (V)
IDD vs. VDD (CL = 4.7nF)
Both Drivers Switching
40 35 30 160 140
IDD vs. VDD (CL = 4.7nF)
Both Drivers Switching
12
Output Rise Time vs. VDD
2.2nF
10 8 6 4 2 0
200kHz
120
2MHz
1MHz
IDD (mA)
25 20 15 10 5 0 4 6 8 10 12 14 16 18
100 80 60 40
Output Rise Time (ns)
IDD (mA)
1nF
100kHz
500kHz
470pF
50kHz
20 0 4 6 8 10 12 14 16 18
4
6
8
10
12
14
16
18
VDD (V)
VDD (V)
VDD (V)
Output Rise Time vs. VDD
40
18 16 14 12 10 8 6 4 2 0
Output Fall Time vs. VDD
50 45 40 35 30 25 20 15 10 5 0 4 6 8 10 12 14 16 18 20 4
Output Fall Time vs. VDD
Output Rise Time (ns)
Output Fall Time (ns)
10nF
30 25 20 15 10 5 0 4 6 8 10 12 14 16 18
Output Fall Time (ns)
35
2.2nF
10nF
4.7nF
1nF
4.7nF
470pF
6
8
10
12
14
16
18
VDD (V)
VDD (V)
VDD (V)
Propagation Delay (tD1) vs. VDD
30
35
Propagation Delay (tD1) vs. VDD
30
Propagation Delay (tD2) vs. VDD
Propagation Delay (ns)
25 20 15 10 5 0
Propagation Delay (ns)
Propagation Delay (ns)
25 20 15 10 5 0 4 6 8 10 12 14 16 18
30
2.2nF
10nF
25 20 15 10 5 0 4 6 8 10 12 14 16 18
2.2nF
1nF
1nF
4.7nF
470pF
470pF
4
6
8
10
12
14
16
18
VDD (V)
VDD (V)
VDD (V)
June 2009
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Micrel, Inc. Conditions: TA = 25C.
Propagation Delay (tD2) vs. VDD
50
60 50 40 30 20
MIC4223/MIC4224/MIC4225
Output Source Resistance vs. Temperature
IDD = 10mA
40
Output Sink Resistance vs. Temperature
IDD = 10mA VDD = 12V
Propagation Delay (ns)
45 35 30 25 20 15 10 5 0 4 6 8 10 12 14 16 18
10
VDD = 4.5V
10nF
Resistance ()
Resistance ()
40
VDD = 12V
30
VDD = 4.5V
20
4.7nF
VDD = 18V
VDD = 18V
10
-40 -20 0 20 40 60 80 100 120 140
-40
-20
0
20
40
60
80
100 120 140
VDD (V)
Temperature (C)
Temperature (C)
Output Rise Time vs. Temperature
18 20
Output Fall Time vs. Temperature
50
Prop. Delay (Inverting) vs. Temperature
CL = 2nF
40
Output Rise Time (ns)
CL = 2nF
16 14 12
Output Fall Time (ns)
VDD = 4.5V
CL = 2nF
18 16 14 12
VDD = 4.5V
VDD = 4.5V; tD2 VDD = 4.5V; tD1
Delay (ns)
VDD = 12V
30 20 10 0
VDD = 18V
10 8
-40 -20 0 20 40 60
VDD = 12V
VDD = 18V
10 8
VDD = 12V; tD1
VDD = 12V; tD2
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (C)
Temperature (C)
Temperature (C)
Prop. Delay (Non-Inverting) vs. Temperature
50 40
Enable to Output Delay (tD3) vs. Temperature
40 80
Enable to Output Delay (tD4) vs. Temperature
CL = 2nF VDD = 4.5V
CL = 2nF
VDD = 4.5V; tD1 VDD = 4.5V; tD2
CL = 2nF
30 20 10
30 25 20 15
Prop. Delay (ns)
Prop. Delay (ns)
35
VDD = 4.5V
70 60 50 40
Delay (ns)
VDD = 12V
VDD = 18V VDD = 12V
VDD = 12V; tD1
0
-40 -20 0 20 40 60
VDD = 12V; tD2
VDD = 18V
10
80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
30
-40 -20 0 20 40 60 80 100 120 140
Temperature (C)
Temperature (C)
Temperature (C)
June 2009
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MIC4223/MIC4224/MIC4225
Functional Diagram
Logic Table
Enables ENA H H H H L ENB H H H H L Inputs INA L L H H X INB L H L H X MIC4223 OUTA H H L L L OUTB H L H L L MIC4224 OUTA L L H H L OUTB L H L H L MIC4225 OUTA H H L L L OUTB L H L H L
Block Diagram
June 2009
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MIC4223/MIC4224/MIC4225
Functional Description
The MIC4223, MIC4224 and MIC4225 are a family of dual high speed, high current drivers. The drivers come in both inverting and non-inverting versions. Each driver has an enable pin that turns the output off (low) regardless of the input. The MIC4223 is a dual inverting driver. The MIC4224 is a dual non-inverting driver and the MIC4225 contains an inverting and non-inverting driver. Enable Each output has an independent enable pin that forces the output low when the enable pin is driven low. Each enable pin is internally pulled-up to VDD. The outputs are enabled by default if the enable pin is left open. Pulling the enable pin low, below its threshold voltage, forces the output low. A fast propagation delay between the enable and output pins quickly disables the output, which is a requirement during a system fault condition. Input Stage The driver input stage is high impedance, TTL-compatible input stage. The driver's input threshold voltage makes it compatible with TTL and CMOS devices that are powered from supply voltages between 3V and VDD. Hysteresis on the input pin improves noise immunity and prevents input signals with slow rise times from falsely triggering the output. The VDD pin current is slightly higher when the input voltage is above the high level threshold. See the Typical Characteristic graphs for additional information. The input voltage signal may go up to -5V below ground without damage to the driver or cause a latch up condition. Negative input voltages that are 0.7V below ground or greater will increase propagation delay. Output Driver Section A functional diagram of the driver output is shown in Figure 2. The output drive is a parallel combination of MOSFET and Bipolar transistor. For a given silicon area, a bipolar device has a lower on-resistance than an equivalent MOS device. It sources and sinks current more consistently as the voltage across it changes. The low drive impedance of the bipolar allows fast turn-on and turn-off of the external MOSFET. The driver's internal MOSFET gives the output near rail-to-rail drive capability. This ensures a low RDSON for the external MOSFET as well as noise immunity from dv/dt induced glitching.
Figure 2. Output Driver
The slew rate of the output is non-adjustable and depends only on the VDD voltage and how much capacitance is present at the OUTA, B pin. Changing the slew rate at the driver's input pin will not affect the output rise or fall times. The slew rate at the MOSFET gate can be adjusted by adding a resistor between the MOSFET gate and the driver output.
June 2009
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MIC4223/MIC4224/MIC4225
Application Information
Power Dissipation Considerations Power dissipation in the driver can be separated into two areas: Output driver stage dissipation Quiescent current dissipation used to supply the internal logic and control functions. Output Driver Stage Power Dissipation Power dissipation in the driver's output stage is mainly caused by charging and discharging the gate to source and gate to drain capacitance of the external MOSFET. Figure 3 shows a simplified circuit of the MIC4223 driving an external MOSFET.
Figure 4. MOSFET Gate Charge vs. VGS
The energy dissipated during turn-on is calculated as:
E = 1 x Ciss x VGS 2
2
where C iss is the MOSFET' s total gate capacitance but : Q = Cx V so E = 1/2 x Q G x VGS
Figure 3. Functional MOSFET/Driver Diagram
An equivalent amount of energy is dissipated in the driver's sink circuit when the MOSFET turns off. The total energy and power dissipated by the drive components is:
EDRIVER = QG x VGS and PDRIVER =QG xVGS x fS
Dissipation Caused by Switching the External MOSFET Energy from capacitor CVDD is used to charge up the input capacitance of the MOSFET (CGD and CGS). The energy delivered to the MOSFET is dissipated in the upper driver MOSFET and Bipolar impedances. The effective capacitance of CGD and CGS is difficult to calculate since they vary non-linearly with ID, VGS, and VDS. Fortunately, most power MOSFET specifications include a typical graph of total gate charge vs. VGS. Figure 4 shows a typical MOSFET gate charge curve. The graph illustrates that for a gate voltage of 10V, the MOSFET requires about 23.5nC of charge.
Where: EDRIVER is the energy dissipated per switching cycle PDRIVER is the power dissipated by switching the MOSFET on and off QG is the total Gate charge at VGS VGS is the MOSFETs Gate to Source voltage fS is the switching frequency of the Gate drive circuit
June 2009
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Micrel, Inc. Quiescent Current Power Dissipation Quiescent current powers the internal logic, level shifting circuitry and bias for the output drivers. This current is proportional to operating frequency and VDD voltage. The typical characteristic graphs show how supply current varies with switching frequency and supply voltage. The power dissipated by the driver's quiescent current is:
MIC4223/MIC4224/MIC4225
PDISS: GATE Charge vs. Frequency
1.4 VDD=5V 1.2 1.0 PDISS (W) 0.8 0.6
20nC 50nC
40nC
Pdiss quiescent = V DD x I DD
Total Power Dissipation and Thermal Considerations Total package power dissipation equals the power dissipation of each driver caused by driving the external MOSFETs plus the supply current.
30nC
0.4 0.2 0 100k 1M FREQUENCY (Hz)
10nC
10M
PdissTOTAL = Pdissquiescent + PdriverA + PdriverB
The die temperature may be calculated once the total power dissipation is known.
TJ = T A + PdissTOTAL x JA
Figure 5a. PDISS vs. QG and fS for VDD = 5V
JA is the thermal resistance from junction-toambient air (C/W) The following graphs help determine the maximum gate charge that can be driven with respect to switching frequency, supply voltage and ambient temperature. Figure 5a shows the power dissipation in the driver for different values of gate charge with VDD = 5V. Figure 5b shows the power dissipation at VDD = 12V. Figure 5c show the maximum power dissipation for a given ambient temperature for the SOIC and ePAD MSOP packages. The maximum operating frequency of the driver may be limited by the maximum power dissipation of the driver package.
PDISS (W)
Where: TA is the Maximum ambient temperature TJ is the junction temperature (C) PdissTOTAL is the power dissipation of the Driver
PDISS: GATE Charge vs. Frequency
2.0 V =12V 1.8 DD 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 100k
20nC 50nC 40nC 30nC
10nC
1M FREQUENCY (Hz)
10M
Figure 5b. PDISS vs. QG and fS for VDD = 12V
Maximum Power Dissipation
2.0
Power Dissipation (W)
1.5
1.0
0.5
0.0 20 40 60 80 100 120 140
Ambient Temperature (C)
Figure 5c. Maximum PDISS vs. Ambient Temperature
June 2009
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M9999-061109-A (408) 944-0800
Micrel, Inc. Bypass Capacitor Selection Bypass capacitors are required for proper operation by supplying the charge necessary to drive the external MOSFETs as well as minimize the voltage ripple on the supply pins. Ceramic capacitors are recommended because of their low impedance and small size. Z5U type ceramic capacitor dielectrics are not recommended due to the large change in capacitance over temperature and voltage. Manufacturer specifications should be checked to insure voltage and temperature do not reduce the capacitance below the value needed. A minimum value of 1F is required regardless of the MOSFETs being driven. Larger MOSFETs, with their higher input capacitance may require larger decoupling capacitance values for proper operation. The voltage rating of the capacitors depends on the supply voltage, ambient temperature and the voltage derating used for reliability. Placement of the decoupling capacitors is critical. The bypass capacitor for VDD should be placed as close as possible between the VDD and GND pins. The etch connections must be short, wide and direct. The use of a ground plane to minimize connection impedance is recommended. Multiple vias insure a low inductance path and help with power dissipation. Refer to the section on layout and component placement for more information. Grounding, Component Placement and Circuit Layout Nanosecond switching speeds and ampere peak currents in and around the MOSFET driver necessitate proper placement and trace routing of all components. Improper placement may cause degraded noise immunity, false switching and excessive ringing. Figure 6 shows the critical current paths when the driver outputs go high and turn on the external MOSFETs. It also helps demonstrate the need for a low impedance ground plane. Charge needed to turn-on the MOSFET gates comes from the decoupling capacitors CVDD. Current in the gate driver flows from CVDD through the internal driver, into the MOSFET gate and out the Source. The return connection back to the decoupling capacitor is made through the ground plane. Any inductance or resistance in the ground return path causes a voltage spike or ringing to appear on the source of the MOSFET. This voltage works against the gate drive voltage and can either slow down or turn off the MOSFET during the period where it should be turned on.
MIC4223/MIC4224/MIC4225
Figure 6. Driver Turn-On Current Path
Figure 7 shows the critical current paths when the driver outputs go low and turn off the external MOSFETs. Short, low impedance connections are important during turn-off for the same reasons given in the turn-on explanation. Current from the VDD supply replenishes charge in the decoupling capacitor, CVDD.
Figure 7. Driver Turn-Off Current Path
The following circuit guidelines should be adhered to for optimum circuit performance: The VDD bypass capacitor must be placed close to the VDD and ground pins. It is critical that the etch length between the decoupling capacitor and the VDD and GND pins be minimized to reduce pin inductance. Multiple vias in parallel help minimize inductance in the ground and VDD paths. A ground plane is recommended to minimize parasitic inductance and impedance of the return paths. The MIC4223 family of drivers is capable of high peak currents and very fast transition times. Any impedance between the driver, the decoupling capacitors and the external MOSFET will degrade the performance of the circuit. Trace out the high di/dt and dv/dt paths, as shown in Figures 6 and 7 and minimize etch length and loop area for these connections. Minimizing these parameters decreases the parasitic inductance and the radiated EMI generated by fast rise and fall times.
June 2009
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M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Evaluation Board Schematic (SOIC)
SOIC Package
June 2009
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Micrel, Inc.
MIC4223/MIC4224/MIC4225
Bill of Materials (SOIC)
Item C1 C2, C7 or or C4, C5 or or Q1, Q2 C3, R4, C6, R9, R1, R2, R6, R8 R5, R7 U1 or or CRCW12061001FRT1 MIC4223YM MIC4224YM MIC4225YM Vishay(1) Micrel, Inc. Micrel, Inc.
(5)
Part Number VJ0603Y104KXXAT C1608X5R1E105M 06033D105MAT GRM188R61E105KA93 C3216X7R1E105K 12063D105MAT GRM31MR71H105KA01 Si4174DY
Manufacturer Vishay TDK
(1) (2)
Description 0.1F/25V, X7R Ceramic Capacitor, Size 0603 1F/25V, X5R, Ceramic Capacitor, Size 0603 1F/25V, X5R, Ceramic Capacitor, Size 0603 1F/25V, X5R, Ceramic Capacitor, Size 0603 1F/25V, X7R, Ceramic Capacitor, Size 1206 1F/25V, X7R, Ceramic Capacitor, Size 1206 1F/25V, X7R, Ceramic Capacitor, Size 1206 30V N-Channel MOSFET Open location - Size 0603
Qty. 1 2 2 2 2 2 2 2 0
AVX(3) MuRata TDK AVX
(4) (2)
(3)
MuRata(4) Vishay
(1)
1k Resistor, Size 1206 Dual Inverting 4A MOSFET Driver with SOIC Package Dual Non-Inverting 4A MOSFET Driver with SOIC Package Dual Inverting/Non-Inverting 4A MOSFET Driver with SOIC Package
2 1 1 1
Micrel, Inc.(5)
(5)
Notes: 1. Vishay: www.vishay.com 2. TDK: www.tdk.com 3. AVX: www.avx.com 4. MuRata: www.murata.com 5. Micrel, Inc: www.micrel.com
June 2009
14
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
PCB Layout (SOIC)
June 2009
15
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Evaluation Board Schematic (e-PAD MSOP)
ePAD MSOP
June 2009
16
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
PCB Layout (ePAD MSOP)
June 2009
17
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Bill of Materials (ePAD MSOP)
Item C1 C2, C7 or or C4, C5 or or C3, R4, C6, R9, R1, R2, R6, R8 Q1, Q2 R5, R7 U1 or or MIC4225YM
Notes: 1. Vishay: www.vishay.com 2. TDK: www.tdk.com 3. AVX: www.avx.com 4. MuRata: www.murata.com 5. Micrel, Inc: www.micrel.com
Part Number VJ0603Y104KXXAT C1608X5R1E105M 06033D105MAT GRM188R61E105KA93 C3216X7R1E105K 12063D105MAT GRM31MR71H105KA01
Manufacturer Vishay TDK
(1) (2)
Description 0.1F/25V, X7R Ceramic Capacitor, Size 0603 1F/25V, X5R, Ceramic Capacitor, Size 0603 1F/25V, X5R, Ceramic Capacitor, Size 0603 1F/25V, X5R, Ceramic Capacitor, Size 0603 1F/25V, X7R, Ceramic Capacitor, Size 1206 1F/25V, X7R, Ceramic Capacitor, Size 1F/25V, X7R, Ceramic Capacitor, Size Open location - Size 0603
Qty. 1 2 2 2 2 2 2 0
AVX(3) MuRata(4) TDK AVX
(2) (3)
MuRata(4)
Si4174DY CRCW12061001FRT1 MIC4223YMME MIC4224YMME
Vishay(1) Vishay
(1) (5) (5)
30V N-Channel MOSFET 1k Resistor, Size 1206 Dual Inverting 4A MOSFET Driver with ePAD MSOP Package Dual Non-Inverting 4A MOSFET Driver with ePAD MSOP Package Dual Inverting/Non-Inverting 4A MOSFET Driver with ePAD MSOP Package
2 2 1 1 1
Micrel, Inc. Micrel, Inc.
Micrel, Inc.(5)
June 2009
18
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Package Information
8-Pin SOIC (M)
June 2009
19
M9999-061109-A (408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
8-Pin ePAD MSOP (MME)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2009 Micrel, Incorporated.
June 2009
20
M9999-061109-A (408) 944-0800

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